project = j1-papilioduo
vendor = xilinx
family = spartan3s
part = xc6slx9-2-tqg144
# part = xc3s200an-4ftg256
top_module = top
flashsize = 2048

vfiles = ../verilog/xilinx-top.v ../verilog/uart.v ../verilog/j1.v ../verilog/stack.v 

include xilinx.mk
